The present invention relates to an ESD protection circuit for an input/output (I/O) buffer design capable of handling multiple types of signals. More particularly, the present invention relates to an ESD protection circuit capable of functioning with an I/O buffer which can be configured to be compatible with different types of circuitry such as Peripheral Component Interconnect (PCI) circuitry, Gunnings Transceiver Logic (GTL), Emitter Coupled Logic (ECL), Series Stub Terminated Logic (SSTL), or Pseudo Emitter Coupled Logic (PECL) circuitry.
Circuits constructed in accordance with standards such as PCI, GTL, ECL, SSTL or PECL each have different high and low state characteristics. Although some of the states for pi different circuit types will have similar voltage and current requirements, others will be different.
PCI provides a high speed bus interface for PC peripheral I/O and memory and its input and output voltage and current requirements are similar to CMOS. For instance, the high and low voltage states will vary from rail to rail (VDD to VSS), with high impedance low current inputs and outputs.
GTL provides a lower impedance higher current high state, providing a low capacitance output to provide higher speed operation. The transition region for GTL is significantly smaller than for CMOS.
PECL provides a high current low voltage to provide a smaller transition region compared to CMOS to better simulate emitter coupled logic (ECL). The PECL offers a low impedance outputs and a high impedance inputs to be the most suitable choice of logic to drive transmission lines to minimize reflections.
Integrated circuit chips, such as a field programmable gate array (FPGA) chip, or a complex programmable logic device (CPLD), provide functions which may be used in a circuit with components operating with any of the logic types, such as PCI, GTL, ECL, PECL, or SSTL described above. With different logic types controlling an output PAD voltage to operate at different levels, as well as different power supply voltage levels now available on chips, it is desirable to provide reliable ESD protection to clamp the PAD voltage during an ESD event to a value which will not damage transistors operating in the desired mode.
In accordance with the present invention, an input/output buffer circuit is configured to be made compatible with any of a number of logic types, such as PCI, GTL, or PECL, and to operate with different power supply voltage levels, while providing adequate ESD protection based on the desired voltage levels.
In accordance with the present invention, an electrostatic discharge ESD protection circuit is provided which includes a lateral NPN BJT transistor which provides a path to ground during ESD without experiencing the gate oxide damage of a typical MOS type device used in the remainder of the I/o buffer circuitry. Additional Darlington pair connected BJTs connect the pad to the lateral BJT during an ESD event, and do not experience oxide damage. An additional BJT is included to selectively clamp the pad voltage. The pad voltage is clamped to a desired value by controlling fuses to connect diode connected MOS transistors between a power supply connection and the base of the BJT used for clamping the pad voltage.